Hybrid Parameter or h parameter

Transistors is a 2 part network.Input and Output of a transistor are related through 2 equation
\[V_1=h_{11}I_1+h_{12}V_2\]

\[I_2=h_{21}I_1+h_{22}V_2\]


\( \left . \frac{V_1}{I_1}  \right |_{V_2=0} \) derived point impedance when output is short circuited $$h_{i},h_{ie},h_{ib}h_{ic}$$
\( \left . \frac{V_1}{V_2}  \right |_{I_1=0} \) Reverse transfer voltage ratio when input is open circuit
 $$h_{r},h_{re},h_{rb}h_{rc}$$
\( \left . \frac{I_2}{I_1}  \right |_{V_2=0} \) forward current ratio when output is short circuited $$h_{f},h_{fe},h_{fb}h_{fc}$$
\( \left . \frac{I_2}{V_2}  \right |_{I_1=0} \) driving point output admittance when input is open circuit $$h_{o},h_{oe},h_{ob}h_{oc}$$

Equivalent circuit

For CE

\[V_b=h_{ie}I_b+h_{re}V_c\]

\[I_c=h_{fe}I_b+h_{oe}V_c\]

For CC

\[V_b=h_{ic}I_b+h_{rc}V_e\]
\[I_e=h_{fc}I_b+h_{oc}V_e\]

For CB

\[V_e=h_{ib}I_e+h_{rb}V_c\]
\[I_c=h_{fb}I_e+h_{ob}V_c\]


Analysis (using without considering source)

Current Gain
\(A_i=\frac {I_L}{I_I}=\frac {-I_2}{I_1}\)

\(I_2=h_fI_1+h_oV_2\)
\( = h_fI_1+h_oI_LR_L\)
\(I_2 = h_fI_1-h_oI_LR_L\)
\(I_2(1+h+oR_L) = h_fI_1\)
\( {\frac{I_2}{I_1} }= {\frac{h_f}{1+h_oR_L}}\)
\( A_I={\frac{-I_2}{I_1} }= {\frac{-h_f}{1+h_oR_L}}\)
cc
\( A_I= {\frac{-h_{fc}}{1+h_{oc}R_L}}\)
ce
\( A_I= {\frac{-h_{fe}}{1+h_{oe}R_L}}\)
cb
\( A_I= {\frac{-h_{fb}}{1+h_{ob}R_L}}\)
\( 2)Input Resistance(R_i) \)
\( R_i= \frac{v_1}{I_1} \)
\( V_1=h_iI_1+h_rV_2\)
\( V_1=h_iI_1-h_rI_2R_L\)
\( \frac{V_1}{I_1}=h_i-\frac{h_rI_2R_L}{I_1}\)
$$ \bbox[5px,border:2px solid red]
{
 R_i=h_i+h_rA_IR_L
}$$

ce
\( R_i=h_{ie}+h_{re}A_IR_L\)
cc
\( R_i=h_{ic}+h_{rc}A_IR_L\)
cb
\( R_i=h_{ib}+h_{rb}A_IR_L\)

3) \( Voltage Gain (A_v)\)
\( A_v=\frac{V_2}{V_1}\)
\(V_2=-I_2R_L\)
\( A_I=\frac{-I_2}{I_1}\)
\( -I_2={A_II_1}\)
=>\( V_2=A_II_1R_L\)
\( A_v=\frac{V_2}{V_1}=\frac{A_II_1R_L}{V_1}=\frac{A_IR_L}{R_i}\)

$$ \bbox[5px,border:2px solid red]
{
 A_v=\frac{A_II_1R_L}{V_1}=\frac{A_IR_L}{R_i}
}$$

4 )  \( Output Resistance(R_o)\)
\( R_o=\frac{V_2}{I_2}\)
\(I_2= h_fI_1+h_oV_2\)
\( \frac{I_2}{V_2} = \frac{h_fI_1}{V_2}+h_o\)
\( Y_o= \frac{h_fI_1}{V_2}+h_o\)

when \( V_s=0\)

\( (R_s+h_i)I_1+h_rV_2=0\)
\( \frac{I_1}{V_2}=\frac{-h_r}{h_i+R_s}\)
\( Y_o= \frac{-h_fh_r}{h_i+R_s}+h_o\)
\( Y_o= h_o-\frac{h_fh_r}{h_i+R_s}\)   
\( R_o=\frac{1}{Y_o}\) 
Power Gain
\( A_p=A_vA_I\)   

Analysis (using with considering source)

Voltage gain

\( A_{vs}=\frac{V_2}{V_s}=\frac{V_2}{V_1}\frac{V_1}{V_s}\)
\( A_{vs}=A_v\frac{V_1}{V_s}\)

\( V_1=\frac{V_sR_i}{R_i+R_s}\)
=>\( \frac{V_1}{V_s}=\frac{R_i}{R_i+R_s}\)

$$ \bbox[5px,border:2px solid red]{  A_{vs}=\frac{A_vR_i}{R_i+R_s}}$$

Current Gain


\(A_{is}=\frac {I_L}{I_s}=\frac {-I_2}{I_s}=\frac {-I_2}{I_1}\frac {I_1}{I_s}\)
\(A_{is}=A_I\frac {I_1}{I_s}\)

\( I_1=I_s\frac {R_s}{R_s+R_L}\)
\(\frac {I_1}{I_s} = \frac {R_s}{R_s+R_L}\)
$$ \bbox[5px,border:2px solid red]{ A_{is} = A_I \frac {R_s}{R_s+R_L} }$$

Thermal run away

Thermal RunAway

During operation  , temperature of the collector terminal increases ,causing dissipation at the junction (Collector junction), This rise in Ic result increased power dissipation at the junction with consequent rise in temperature  at junction .This form a cumulative process and as a rsults Q point shifts or run away . This shifting of Q point due to heating of collector junction is referred to as thermal run away . If this process of thermal run away is not checked or kept within limit ,it may cause permanent damge to IC.
This can be avoided using

a)Proper removal of heat through radiation
b)Proper design and layout of circuit
c)use of forced air drift
d)Use of heat sink providing increased radiation surface

Three Transistor Biasing

Fixed biased

Input section
Applying kirchoff's vltage law to input side

Vcc=IbRb+Vbe

Ib=(Vcc-Vbe)/Rb

but Vbe<<Vce => Ib=Vcc/Rb

thus for fixed Vcc&Rb , the base current is fixed ,hence collector fixed bias

Output section
Applying Kirchoff's voltage law to output side

Vcc=IcRc+Vce

Vce=Vcc-IcRc

Ic=βIb+(1+β)Icbo
Ic=βIb+Iceo

Iceo=== leakage current
βIb===contribution of input current
β===Current gain

Iceo=(1+β)Icbo

for an ideal contains
Ic=βIb
Stability factor
 \( \left . Ic =  β{\frac{V_{CC}}{R_B}}+(1+β)Icbo\right . \)
differentiating with respect \[I_{icbo}\]
       \( \left . s =  β{\frac{dI_{C}}{dI_{cbo}}} = β+1 \right . \)


Reason why fixed bias is never used 
Any rise in temperature results in rise in Icbo and Iceo ,Hence collector current Ic rises resulting in rise in collector junction temperature , this is a cumulative process and collector current goes on increasing


Collector to base bias 

Input section
Applying kvl to input side

Vcc=(Ic+Ib)Rc+IbRb+Vbe

Ib=[(Vcc-IcRc)-Vbe]/(Rc+Rb)

Output section
applying kvl to output side

Vcc=(Ic+Ib)Rc+Vce

since Ib<<Ic

=> Vce=Vcc-IcRc

Ib=(Vce-Vbe)/(Rc+Rb)

As temperature increase ,leakage current Iceo rises

Ic=(βIb+Iceo)↑
Vce=Vcc-IcRc ↓

It will decrease Ib also .This will result in reduced Ic so this stabilise operating point

Self bias /Emitter bias /Voltage divider bias/potential divider bias

Vb=VccR2/(R1+R2)
Rb=R1||R2











This biasing method is most popularly used because it provide excellent operating point  stability ,When temperature increases ,leakage current increases ,thus voltage across Re increases, This will reverse bias the base emitter junction ,But R1-R2 combination across Vcc produces a positive voltage Vb at the base relative to emitter

Rb=R1R2/(R1+R2)
Vb=VccR2/(R1+R2)

applying kvl in output side

Vcc=IcRc+Vce+(Ic+Ib)Re

Ve=(Ic+Ib)Re

Vbe=Vb-Ve

Ic=βIb+Iceo

Stabilization 
Any rise in temperature T, cause a rise in Icbo and hence rise in Ic .This increased current through Re cause increase in DC voltage drop across Re and reduces te E-B forward bias , reducing the base current and thus collector current Ic. This reduction in Ic tends to cancel the rise in Ic cause by temperature rise . and thus operating point stability is improved

Operating point and Load line

Operating point and Load line

Vcc=IcRc+Vce

for Vce=0
Ic=Vcc/Rc

for Ic=0
Vce=Vcc

The line joining between Vcc/Rc and Vcc is known as static load line/DC load line. the point at which the dc load line meets with the characteristic line in the active region is known as Q point / quiescent point/operating point
The parallel line passing through q point is the AC load line . The transistor characteristic reverse that the transistor operation is most linear when it is constrained to operate in its active region by providing dc potential and current by using external sources
An important selected operating point results in a output signal wave form is not a faithful reproduction of the input signal waveform ,such operating point unsatisfactory and should be re positioned on the collector point in vital for linear amplification

Bias stability
the operating point stability may be influenced by the following characteristics factors
1)Change in trasistor
2)Thermal instability(Change in temperature)

Transistor Replacement

Transistor of particular type manufactures by the same company come out of production with different values of several parameters . Hence when a transistor in a given circuit is replaced by another of the same type, there is some variation in transistor parameters

Thermal stability

Ic=βIb+(1+β)Iceo
When there is a change in temperature ,there is a marked change in reverse saturation current Ico ,thus for every 10 degree rise in temperature Ico get double

Biasing(Need for biasing)

Derived features of biasing method used as transistor biasing circuits should be:-

1)To establish conviniently the operating point in the middle of active region of chara
2)To make the operating point independent of temperature variation
3)To establish the collector current against temperature variation